General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control
SYSCTL_DCGCGPIO_D0 | GPIO Port A Deep-Sleep Mode Clock Gating Control |
SYSCTL_DCGCGPIO_D1 | GPIO Port B Deep-Sleep Mode Clock Gating Control |
SYSCTL_DCGCGPIO_D2 | GPIO Port C Deep-Sleep Mode Clock Gating Control |
SYSCTL_DCGCGPIO_D3 | GPIO Port D Deep-Sleep Mode Clock Gating Control |
SYSCTL_DCGCGPIO_D4 | GPIO Port E Deep-Sleep Mode Clock Gating Control |
SYSCTL_DCGCGPIO_D5 | GPIO Port F Deep-Sleep Mode Clock Gating Control |
SYSCTL_DCGCGPIO_D6 | GPIO Port G Deep-Sleep Mode Clock Gating Control |
SYSCTL_DCGCGPIO_D7 | GPIO Port H Deep-Sleep Mode Clock Gating Control |
SYSCTL_DCGCGPIO_D8 | GPIO Port J Deep-Sleep Mode Clock Gating Control |
SYSCTL_DCGCGPIO_D9 | GPIO Port K Deep-Sleep Mode Clock Gating Control |
SYSCTL_DCGCGPIO_D10 | GPIO Port L Deep-Sleep Mode Clock Gating Control |
SYSCTL_DCGCGPIO_D11 | GPIO Port M Deep-Sleep Mode Clock Gating Control |
SYSCTL_DCGCGPIO_D12 | GPIO Port N Deep-Sleep Mode Clock Gating Control |
SYSCTL_DCGCGPIO_D13 | GPIO Port P Deep-Sleep Mode Clock Gating Control |